--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: K.31
--  \   \         Application: netgen
--  /   /         Filename: threshold_timesim.vhd
-- /___/   /\     Timestamp: Tue Jan 20 22:27:41 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 4 -pcf threshold.pcf -rpw 100 -tpw 0 -ar Structure -tm threshold -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim threshold.ncd threshold_timesim.vhd 
-- Device	: 3s200tq144-4 (PRODUCTION 1.39 2008-01-09)
-- Input file	: threshold.ncd
-- Output file	: /home/remy/robotter/robotter/trunk/eurobot/fpgas/camera/ISE/netgen/par/threshold_timesim.vhd
-- # of Entities	: 1
-- Design Name	: threshold
-- Xilinx	: /opt/Xilinx/10.1/ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity threshold is
  port (
    clk_i : in STD_LOGIC := 'X'; 
    valid_i : in STD_LOGIC := 'X'; 
    result_o : out STD_LOGIC_VECTOR ( 15 downto 0 ); 
    H_i : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    adress_i : in STD_LOGIC_VECTOR ( 9 downto 0 ); 
    Y_i : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    value_i : in STD_LOGIC_VECTOR ( 15 downto 0 ) 
  );
end threshold;

architecture Structure of threshold is
  signal adress_i_3_IBUF_404 : STD_LOGIC; 
  signal adress_i_4_IBUF_405 : STD_LOGIC; 
  signal adress_i_5_IBUF_406 : STD_LOGIC; 
  signal adress_i_6_IBUF_407 : STD_LOGIC; 
  signal adress_i_7_IBUF_408 : STD_LOGIC; 
  signal value_i_10_IBUF_409 : STD_LOGIC; 
  signal adress_i_8_IBUF_410 : STD_LOGIC; 
  signal value_i_11_IBUF_411 : STD_LOGIC; 
  signal adress_i_9_IBUF_412 : STD_LOGIC; 
  signal H_i_0_IBUF_413 : STD_LOGIC; 
  signal value_i_12_IBUF_414 : STD_LOGIC; 
  signal H_i_1_IBUF_415 : STD_LOGIC; 
  signal value_i_13_IBUF_416 : STD_LOGIC; 
  signal H_i_2_IBUF_417 : STD_LOGIC; 
  signal value_i_14_IBUF_418 : STD_LOGIC; 
  signal H_i_3_IBUF_419 : STD_LOGIC; 
  signal value_i_15_IBUF_420 : STD_LOGIC; 
  signal H_i_4_IBUF_421 : STD_LOGIC; 
  signal H_i_5_IBUF_422 : STD_LOGIC; 
  signal H_i_6_IBUF_423 : STD_LOGIC; 
  signal H_i_7_IBUF_424 : STD_LOGIC; 
  signal H_i_8_IBUF_425 : STD_LOGIC; 
  signal value_i_0_IBUF_426 : STD_LOGIC; 
  signal value_i_1_IBUF_427 : STD_LOGIC; 
  signal value_i_2_IBUF_428 : STD_LOGIC; 
  signal value_i_3_IBUF_430 : STD_LOGIC; 
  signal value_i_4_IBUF_431 : STD_LOGIC; 
  signal result_o_10_432 : STD_LOGIC; 
  signal value_i_5_IBUF_433 : STD_LOGIC; 
  signal result_o_11_434 : STD_LOGIC; 
  signal value_i_6_IBUF_435 : STD_LOGIC; 
  signal result_o_12_436 : STD_LOGIC; 
  signal value_i_7_IBUF_437 : STD_LOGIC; 
  signal result_o_13_438 : STD_LOGIC; 
  signal Y_i_0_IBUF_439 : STD_LOGIC; 
  signal value_i_8_IBUF_440 : STD_LOGIC; 
  signal result_o_14_441 : STD_LOGIC; 
  signal Y_i_1_IBUF_442 : STD_LOGIC; 
  signal value_i_9_IBUF_443 : STD_LOGIC; 
  signal result_o_0_444 : STD_LOGIC; 
  signal result_o_15_445 : STD_LOGIC; 
  signal Y_i_2_IBUF_446 : STD_LOGIC; 
  signal result_o_1_447 : STD_LOGIC; 
  signal Y_i_3_IBUF_448 : STD_LOGIC; 
  signal result_o_2_449 : STD_LOGIC; 
  signal Y_i_4_IBUF_450 : STD_LOGIC; 
  signal result_o_3_451 : STD_LOGIC; 
  signal Y_i_5_IBUF_452 : STD_LOGIC; 
  signal result_o_4_453 : STD_LOGIC; 
  signal Y_i_6_IBUF_454 : STD_LOGIC; 
  signal result_o_5_455 : STD_LOGIC; 
  signal Y_i_7_IBUF_456 : STD_LOGIC; 
  signal result_o_6_457 : STD_LOGIC; 
  signal Y_i_8_IBUF_458 : STD_LOGIC; 
  signal result_o_7_459 : STD_LOGIC; 
  signal result_o_8_460 : STD_LOGIC; 
  signal result_o_9_461 : STD_LOGIC; 
  signal valid_i_IBUF_462 : STD_LOGIC; 
  signal adress_i_0_IBUF_463 : STD_LOGIC; 
  signal adress_i_1_IBUF_464 : STD_LOGIC; 
  signal adress_i_2_IBUF_465 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal clk_i_BUFGP : STD_LOGIC; 
  signal H_enable_B_s_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal Y_enable_B_s_0 : STD_LOGIC; 
  signal adress_i_3_INBUF : STD_LOGIC; 
  signal adress_i_4_INBUF : STD_LOGIC; 
  signal adress_i_5_INBUF : STD_LOGIC; 
  signal adress_i_6_INBUF : STD_LOGIC; 
  signal adress_i_7_INBUF : STD_LOGIC; 
  signal value_i_10_INBUF : STD_LOGIC; 
  signal adress_i_8_INBUF : STD_LOGIC; 
  signal value_i_11_INBUF : STD_LOGIC; 
  signal adress_i_9_INBUF : STD_LOGIC; 
  signal H_i_0_INBUF : STD_LOGIC; 
  signal value_i_12_INBUF : STD_LOGIC; 
  signal H_i_1_INBUF : STD_LOGIC; 
  signal value_i_13_INBUF : STD_LOGIC; 
  signal H_i_2_INBUF : STD_LOGIC; 
  signal value_i_14_INBUF : STD_LOGIC; 
  signal H_i_3_INBUF : STD_LOGIC; 
  signal value_i_15_INBUF : STD_LOGIC; 
  signal H_i_4_INBUF : STD_LOGIC; 
  signal H_i_5_INBUF : STD_LOGIC; 
  signal H_i_6_INBUF : STD_LOGIC; 
  signal H_i_7_INBUF : STD_LOGIC; 
  signal H_i_8_INBUF : STD_LOGIC; 
  signal value_i_0_INBUF : STD_LOGIC; 
  signal value_i_1_INBUF : STD_LOGIC; 
  signal value_i_2_INBUF : STD_LOGIC; 
  signal clk_i_INBUF : STD_LOGIC; 
  signal value_i_3_INBUF : STD_LOGIC; 
  signal value_i_4_INBUF : STD_LOGIC; 
  signal result_o_10_O : STD_LOGIC; 
  signal value_i_5_INBUF : STD_LOGIC; 
  signal result_o_11_O : STD_LOGIC; 
  signal value_i_6_INBUF : STD_LOGIC; 
  signal result_o_12_O : STD_LOGIC; 
  signal value_i_7_INBUF : STD_LOGIC; 
  signal result_o_13_O : STD_LOGIC; 
  signal Y_i_0_INBUF : STD_LOGIC; 
  signal value_i_8_INBUF : STD_LOGIC; 
  signal result_o_14_O : STD_LOGIC; 
  signal Y_i_1_INBUF : STD_LOGIC; 
  signal value_i_9_INBUF : STD_LOGIC; 
  signal result_o_0_O : STD_LOGIC; 
  signal result_o_15_O : STD_LOGIC; 
  signal Y_i_2_INBUF : STD_LOGIC; 
  signal result_o_1_O : STD_LOGIC; 
  signal Y_i_3_INBUF : STD_LOGIC; 
  signal result_o_2_O : STD_LOGIC; 
  signal Y_i_4_INBUF : STD_LOGIC; 
  signal result_o_3_O : STD_LOGIC; 
  signal Y_i_5_INBUF : STD_LOGIC; 
  signal result_o_4_O : STD_LOGIC; 
  signal Y_i_6_INBUF : STD_LOGIC; 
  signal result_o_5_O : STD_LOGIC; 
  signal Y_i_7_INBUF : STD_LOGIC; 
  signal result_o_6_O : STD_LOGIC; 
  signal Y_i_8_INBUF : STD_LOGIC; 
  signal result_o_7_O : STD_LOGIC; 
  signal result_o_8_O : STD_LOGIC; 
  signal result_o_9_O : STD_LOGIC; 
  signal valid_i_INBUF : STD_LOGIC; 
  signal adress_i_0_INBUF : STD_LOGIC; 
  signal adress_i_1_INBUF : STD_LOGIC; 
  signal adress_i_2_INBUF : STD_LOGIC; 
  signal clk_i_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal clk_i_BUFGP_BUFG_I0_INV : STD_LOGIC; 
  signal RAMB16_H_inst_DOPB1 : STD_LOGIC; 
  signal RAMB16_H_inst_DOPB0 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB15 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB14 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB13 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB12 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB11 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB10 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB9 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB8 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB7 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB6 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB5 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB4 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB3 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB2 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB1 : STD_LOGIC; 
  signal RAMB16_H_inst_DOB0 : STD_LOGIC; 
  signal RAMB16_H_inst_DOPA1 : STD_LOGIC; 
  signal RAMB16_H_inst_DOPA0 : STD_LOGIC; 
  signal RAMB16_H_inst_DIPA1 : STD_LOGIC; 
  signal RAMB16_H_inst_DIPA0 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA15 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA14 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA13 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA12 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA11 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA10 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA9 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA8 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA7 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA6 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA5 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA4 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA3 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA2 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA1 : STD_LOGIC; 
  signal RAMB16_H_inst_DIA0 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOPB1 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOPB0 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB15 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB14 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB13 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB12 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB11 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB10 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB9 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB8 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB7 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB6 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB5 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB4 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB3 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB2 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB1 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOB0 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOPA1 : STD_LOGIC; 
  signal RAMB16_Y_inst_DOPA0 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIPA1 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIPA0 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA15 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA14 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA13 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA12 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA11 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA10 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA9 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA8 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA7 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA6 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA5 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA4 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA3 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA2 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA1 : STD_LOGIC; 
  signal RAMB16_Y_inst_DIA0 : STD_LOGIC; 
  signal result_o_1_DXMUX_1142 : STD_LOGIC; 
  signal result_o_1_DYMUX_1129 : STD_LOGIC; 
  signal result_o_1_CLKINV_1119 : STD_LOGIC; 
  signal result_o_3_DXMUX_1176 : STD_LOGIC; 
  signal result_o_3_DYMUX_1163 : STD_LOGIC; 
  signal result_o_3_CLKINV_1153 : STD_LOGIC; 
  signal result_o_5_DXMUX_1210 : STD_LOGIC; 
  signal result_o_5_DYMUX_1197 : STD_LOGIC; 
  signal result_o_5_CLKINV_1187 : STD_LOGIC; 
  signal result_o_7_DXMUX_1244 : STD_LOGIC; 
  signal result_o_7_DYMUX_1231 : STD_LOGIC; 
  signal result_o_7_CLKINV_1221 : STD_LOGIC; 
  signal result_o_9_DXMUX_1278 : STD_LOGIC; 
  signal result_o_9_DYMUX_1265 : STD_LOGIC; 
  signal result_o_9_CLKINV_1255 : STD_LOGIC; 
  signal result_o_11_DXMUX_1312 : STD_LOGIC; 
  signal result_o_11_DYMUX_1299 : STD_LOGIC; 
  signal result_o_11_CLKINV_1289 : STD_LOGIC; 
  signal result_o_13_DXMUX_1346 : STD_LOGIC; 
  signal result_o_13_DYMUX_1333 : STD_LOGIC; 
  signal result_o_13_CLKINV_1323 : STD_LOGIC; 
  signal result_o_15_DXMUX_1380 : STD_LOGIC; 
  signal result_o_15_DYMUX_1367 : STD_LOGIC; 
  signal result_o_15_CLKINV_1357 : STD_LOGIC; 
  signal Y_enable_B_s : STD_LOGIC; 
  signal H_enable_B_s : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal H_thres_s : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal Y_thres_s : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal result_o_and0000 : STD_LOGIC_VECTOR ( 15 downto 0 ); 
begin
  adress_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD182",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(3),
      O => adress_i_3_INBUF
    );
  adress_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD182",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_3_INBUF,
      O => adress_i_3_IBUF_404
    );
  adress_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(4),
      O => adress_i_4_INBUF
    );
  adress_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD19",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_4_INBUF,
      O => adress_i_4_IBUF_405
    );
  adress_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD185",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(5),
      O => adress_i_5_INBUF
    );
  adress_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD185",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_5_INBUF,
      O => adress_i_5_IBUF_406
    );
  adress_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD22",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(6),
      O => adress_i_6_INBUF
    );
  adress_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD22",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_6_INBUF,
      O => adress_i_6_IBUF_407
    );
  adress_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD174",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(7),
      O => adress_i_7_INBUF
    );
  adress_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD174",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_7_INBUF,
      O => adress_i_7_IBUF_408
    );
  value_i_10_IBUF : X_BUF
    generic map(
      LOC => "PAD82",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(10),
      O => value_i_10_INBUF
    );
  value_i_10_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD82",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_10_INBUF,
      O => value_i_10_IBUF_409
    );
  adress_i_8_IBUF : X_BUF
    generic map(
      LOC => "PAD23",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(8),
      O => adress_i_8_INBUF
    );
  adress_i_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD23",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_8_INBUF,
      O => adress_i_8_IBUF_410
    );
  value_i_11_IBUF : X_BUF
    generic map(
      LOC => "PAD61",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(11),
      O => value_i_11_INBUF
    );
  value_i_11_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD61",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_11_INBUF,
      O => value_i_11_IBUF_411
    );
  adress_i_9_IBUF : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(9),
      O => adress_i_9_INBUF
    );
  adress_i_9_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD98",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_9_INBUF,
      O => adress_i_9_IBUF_412
    );
  H_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD29",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(0),
      O => H_i_0_INBUF
    );
  H_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD29",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_0_INBUF,
      O => H_i_0_IBUF_413
    );
  value_i_12_IBUF : X_BUF
    generic map(
      LOC => "PAD59",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(12),
      O => value_i_12_INBUF
    );
  value_i_12_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD59",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_12_INBUF,
      O => value_i_12_IBUF_414
    );
  H_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD28",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(1),
      O => H_i_1_INBUF
    );
  H_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD28",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_1_INBUF,
      O => H_i_1_IBUF_415
    );
  value_i_13_IBUF : X_BUF
    generic map(
      LOC => "PAD60",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(13),
      O => value_i_13_INBUF
    );
  value_i_13_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD60",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_13_INBUF,
      O => value_i_13_IBUF_416
    );
  H_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD27",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(2),
      O => H_i_2_INBUF
    );
  H_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD27",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_2_INBUF,
      O => H_i_2_IBUF_417
    );
  value_i_14_IBUF : X_BUF
    generic map(
      LOC => "PAD51",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(14),
      O => value_i_14_INBUF
    );
  value_i_14_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD51",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_14_INBUF,
      O => value_i_14_IBUF_418
    );
  H_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD196",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(3),
      O => H_i_3_INBUF
    );
  H_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD196",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_3_INBUF,
      O => H_i_3_IBUF_419
    );
  value_i_15_IBUF : X_BUF
    generic map(
      LOC => "PAD25",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(15),
      O => value_i_15_INBUF
    );
  value_i_15_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD25",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_15_INBUF,
      O => value_i_15_IBUF_420
    );
  H_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD195",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(4),
      O => H_i_4_INBUF
    );
  H_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD195",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_4_INBUF,
      O => H_i_4_IBUF_421
    );
  H_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD186",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(5),
      O => H_i_5_INBUF
    );
  H_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD186",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_5_INBUF,
      O => H_i_5_IBUF_422
    );
  H_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD188",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(6),
      O => H_i_6_INBUF
    );
  H_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD188",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_6_INBUF,
      O => H_i_6_IBUF_423
    );
  H_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD187",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(7),
      O => H_i_7_INBUF
    );
  H_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD187",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_7_INBUF,
      O => H_i_7_IBUF_424
    );
  H_i_8_IBUF : X_BUF
    generic map(
      LOC => "PAD189",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i(8),
      O => H_i_8_INBUF
    );
  H_i_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD189",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_i_8_INBUF,
      O => H_i_8_IBUF_425
    );
  value_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD111",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(0),
      O => value_i_0_INBUF
    );
  value_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD111",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_0_INBUF,
      O => value_i_0_IBUF_426
    );
  value_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD91",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(1),
      O => value_i_1_INBUF
    );
  value_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD91",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_1_INBUF,
      O => value_i_1_IBUF_427
    );
  value_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD90",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(2),
      O => value_i_2_INBUF
    );
  value_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD90",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_2_INBUF,
      O => value_i_2_IBUF_428
    );
  clk_i_BUFGP_IBUFG : X_BUF
    generic map(
      LOC => "PAD126",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i,
      O => clk_i_INBUF
    );
  value_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD66",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(3),
      O => value_i_3_INBUF
    );
  value_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD66",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_3_INBUF,
      O => value_i_3_IBUF_430
    );
  value_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD64",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(4),
      O => value_i_4_INBUF
    );
  value_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD64",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_4_INBUF,
      O => value_i_4_IBUF_431
    );
  result_o_10_OBUF : X_OBUF
    generic map(
      LOC => "PAD50"
    )
    port map (
      I => result_o_10_O,
      O => result_o(10)
    );
  value_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD65",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(5),
      O => value_i_5_INBUF
    );
  value_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD65",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_5_INBUF,
      O => value_i_5_IBUF_433
    );
  result_o_11_OBUF : X_OBUF
    generic map(
      LOC => "PAD49"
    )
    port map (
      I => result_o_11_O,
      O => result_o(11)
    );
  value_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD81",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(6),
      O => value_i_6_INBUF
    );
  value_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD81",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_6_INBUF,
      O => value_i_6_IBUF_435
    );
  result_o_12_OBUF : X_OBUF
    generic map(
      LOC => "PAD39"
    )
    port map (
      I => result_o_12_O,
      O => result_o(12)
    );
  value_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD63",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(7),
      O => value_i_7_INBUF
    );
  value_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD63",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_7_INBUF,
      O => value_i_7_IBUF_437
    );
  result_o_13_OBUF : X_OBUF
    generic map(
      LOC => "PAD38"
    )
    port map (
      I => result_o_13_O,
      O => result_o(13)
    );
  Y_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD83",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(0),
      O => Y_i_0_INBUF
    );
  Y_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD83",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_0_INBUF,
      O => Y_i_0_IBUF_439
    );
  value_i_8_IBUF : X_BUF
    generic map(
      LOC => "PAD62",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(8),
      O => value_i_8_INBUF
    );
  value_i_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD62",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_8_INBUF,
      O => value_i_8_IBUF_440
    );
  result_o_14_OBUF : X_OBUF
    generic map(
      LOC => "PAD37"
    )
    port map (
      I => result_o_14_O,
      O => result_o(14)
    );
  Y_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD73",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(1),
      O => Y_i_1_INBUF
    );
  Y_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD73",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_1_INBUF,
      O => Y_i_1_IBUF_442
    );
  value_i_9_IBUF : X_BUF
    generic map(
      LOC => "PAD76",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i(9),
      O => value_i_9_INBUF
    );
  value_i_9_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD76",
      PATHPULSE => 757 ps
    )
    port map (
      I => value_i_9_INBUF,
      O => value_i_9_IBUF_443
    );
  result_o_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD75"
    )
    port map (
      I => result_o_0_O,
      O => result_o(0)
    );
  result_o_15_OBUF : X_OBUF
    generic map(
      LOC => "PAD52"
    )
    port map (
      I => result_o_15_O,
      O => result_o(15)
    );
  Y_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD89",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(2),
      O => Y_i_2_INBUF
    );
  Y_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD89",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_2_INBUF,
      O => Y_i_2_IBUF_446
    );
  result_o_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD74"
    )
    port map (
      I => result_o_1_O,
      O => result_o(1)
    );
  Y_i_3_IBUF : X_BUF
    generic map(
      LOC => "PAD84",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(3),
      O => Y_i_3_INBUF
    );
  Y_i_3_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD84",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_3_INBUF,
      O => Y_i_3_IBUF_448
    );
  result_o_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD180"
    )
    port map (
      I => result_o_2_O,
      O => result_o(2)
    );
  Y_i_4_IBUF : X_BUF
    generic map(
      LOC => "PAD88",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(4),
      O => Y_i_4_INBUF
    );
  Y_i_4_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD88",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_4_INBUF,
      O => Y_i_4_IBUF_450
    );
  result_o_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD179"
    )
    port map (
      I => result_o_3_O,
      O => result_o(3)
    );
  Y_i_5_IBUF : X_BUF
    generic map(
      LOC => "PAD85",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(5),
      O => Y_i_5_INBUF
    );
  Y_i_5_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD85",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_5_INBUF,
      O => Y_i_5_IBUF_452
    );
  result_o_4_OBUF : X_OBUF
    generic map(
      LOC => "PAD20"
    )
    port map (
      I => result_o_4_O,
      O => result_o(4)
    );
  Y_i_6_IBUF : X_BUF
    generic map(
      LOC => "PAD68",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(6),
      O => Y_i_6_INBUF
    );
  Y_i_6_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD68",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_6_INBUF,
      O => Y_i_6_IBUF_454
    );
  result_o_5_OBUF : X_OBUF
    generic map(
      LOC => "PAD181"
    )
    port map (
      I => result_o_5_O,
      O => result_o(5)
    );
  Y_i_7_IBUF : X_BUF
    generic map(
      LOC => "PAD86",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(7),
      O => Y_i_7_INBUF
    );
  Y_i_7_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD86",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_7_INBUF,
      O => Y_i_7_IBUF_456
    );
  result_o_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD13"
    )
    port map (
      I => result_o_6_O,
      O => result_o(6)
    );
  Y_i_8_IBUF : X_BUF
    generic map(
      LOC => "PAD67",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i(8),
      O => Y_i_8_INBUF
    );
  Y_i_8_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD67",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_i_8_INBUF,
      O => Y_i_8_IBUF_458
    );
  result_o_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD30"
    )
    port map (
      I => result_o_7_O,
      O => result_o(7)
    );
  result_o_8_OBUF : X_OBUF
    generic map(
      LOC => "PAD3"
    )
    port map (
      I => result_o_8_O,
      O => result_o(8)
    );
  result_o_9_OBUF : X_OBUF
    generic map(
      LOC => "PAD2"
    )
    port map (
      I => result_o_9_O,
      O => result_o(9)
    );
  valid_i_IBUF : X_BUF
    generic map(
      LOC => "PAD87",
      PATHPULSE => 757 ps
    )
    port map (
      I => valid_i,
      O => valid_i_INBUF
    );
  valid_i_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD87",
      PATHPULSE => 757 ps
    )
    port map (
      I => valid_i_INBUF,
      O => valid_i_IBUF_462
    );
  adress_i_0_IBUF : X_BUF
    generic map(
      LOC => "PAD173",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(0),
      O => adress_i_0_INBUF
    );
  adress_i_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD173",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_0_INBUF,
      O => adress_i_0_IBUF_463
    );
  adress_i_1_IBUF : X_BUF
    generic map(
      LOC => "PAD184",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(1),
      O => adress_i_1_INBUF
    );
  adress_i_1_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD184",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_1_INBUF,
      O => adress_i_1_IBUF_464
    );
  adress_i_2_IBUF : X_BUF
    generic map(
      LOC => "PAD183",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i(2),
      O => adress_i_2_INBUF
    );
  adress_i_2_IFF_IMUX : X_BUF
    generic map(
      LOC => "PAD183",
      PATHPULSE => 757 ps
    )
    port map (
      I => adress_i_2_INBUF,
      O => adress_i_2_IBUF_465
    );
  clk_i_BUFGP_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX2"
    )
    port map (
      I0 => clk_i_BUFGP_BUFG_I0_INV,
      I1 => GND,
      S => clk_i_BUFGP_BUFG_S_INVNOT,
      O => clk_i_BUFGP
    );
  clk_i_BUFGP_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX2",
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_i_BUFGP_BUFG_S_INVNOT
    );
  clk_i_BUFGP_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX2",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_INBUF,
      O => clk_i_BUFGP_BUFG_I0_INV
    );
  RAMB16_H_inst : X_RAMB16_S18_S18
    generic map(
      INIT_A => X"00000",
      INIT_B => X"00000",
      SRVAL_A => X"00000",
      SRVAL_B => X"00000",
      SIM_COLLISION_CHECK => "ALL",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      LOC => "RAMB16_X1Y4",
      SETUP_ALL => 484 ps,
      SETUP_READ_FIRST => 484 ps
    )
    port map (
      CLKA => clk_i_BUFGP,
      CLKB => clk_i_BUFGP,
      ENA => GLOBAL_LOGIC1,
      ENB => H_enable_B_s_0,
      SSRA => GLOBAL_LOGIC0,
      SSRB => GLOBAL_LOGIC0,
      WEA => GLOBAL_LOGIC0,
      WEB => GLOBAL_LOGIC1,
      ADDRA(9) => GLOBAL_LOGIC0,
      ADDRA(8) => H_i_8_IBUF_425,
      ADDRA(7) => H_i_7_IBUF_424,
      ADDRA(6) => H_i_6_IBUF_423,
      ADDRA(5) => H_i_5_IBUF_422,
      ADDRA(4) => H_i_4_IBUF_421,
      ADDRA(3) => H_i_3_IBUF_419,
      ADDRA(2) => H_i_2_IBUF_417,
      ADDRA(1) => H_i_1_IBUF_415,
      ADDRA(0) => H_i_0_IBUF_413,
      ADDRB(9) => GLOBAL_LOGIC0,
      ADDRB(8) => adress_i_8_IBUF_410,
      ADDRB(7) => adress_i_7_IBUF_408,
      ADDRB(6) => adress_i_6_IBUF_407,
      ADDRB(5) => adress_i_5_IBUF_406,
      ADDRB(4) => adress_i_4_IBUF_405,
      ADDRB(3) => adress_i_3_IBUF_404,
      ADDRB(2) => adress_i_2_IBUF_465,
      ADDRB(1) => adress_i_1_IBUF_464,
      ADDRB(0) => adress_i_0_IBUF_463,
      DIA(15) => RAMB16_H_inst_DIA15,
      DIA(14) => RAMB16_H_inst_DIA14,
      DIA(13) => RAMB16_H_inst_DIA13,
      DIA(12) => RAMB16_H_inst_DIA12,
      DIA(11) => RAMB16_H_inst_DIA11,
      DIA(10) => RAMB16_H_inst_DIA10,
      DIA(9) => RAMB16_H_inst_DIA9,
      DIA(8) => RAMB16_H_inst_DIA8,
      DIA(7) => RAMB16_H_inst_DIA7,
      DIA(6) => RAMB16_H_inst_DIA6,
      DIA(5) => RAMB16_H_inst_DIA5,
      DIA(4) => RAMB16_H_inst_DIA4,
      DIA(3) => RAMB16_H_inst_DIA3,
      DIA(2) => RAMB16_H_inst_DIA2,
      DIA(1) => RAMB16_H_inst_DIA1,
      DIA(0) => RAMB16_H_inst_DIA0,
      DIPA(1) => RAMB16_H_inst_DIPA1,
      DIPA(0) => RAMB16_H_inst_DIPA0,
      DIB(15) => value_i_15_IBUF_420,
      DIB(14) => value_i_14_IBUF_418,
      DIB(13) => value_i_13_IBUF_416,
      DIB(12) => value_i_12_IBUF_414,
      DIB(11) => value_i_11_IBUF_411,
      DIB(10) => value_i_10_IBUF_409,
      DIB(9) => value_i_9_IBUF_443,
      DIB(8) => value_i_8_IBUF_440,
      DIB(7) => value_i_7_IBUF_437,
      DIB(6) => value_i_6_IBUF_435,
      DIB(5) => value_i_5_IBUF_433,
      DIB(4) => value_i_4_IBUF_431,
      DIB(3) => value_i_3_IBUF_430,
      DIB(2) => value_i_2_IBUF_428,
      DIB(1) => value_i_1_IBUF_427,
      DIB(0) => value_i_0_IBUF_426,
      DIPB(1) => GLOBAL_LOGIC0,
      DIPB(0) => GLOBAL_LOGIC0,
      DOA(15) => H_thres_s(15),
      DOA(14) => H_thres_s(14),
      DOA(13) => H_thres_s(13),
      DOA(12) => H_thres_s(12),
      DOA(11) => H_thres_s(11),
      DOA(10) => H_thres_s(10),
      DOA(9) => H_thres_s(9),
      DOA(8) => H_thres_s(8),
      DOA(7) => H_thres_s(7),
      DOA(6) => H_thres_s(6),
      DOA(5) => H_thres_s(5),
      DOA(4) => H_thres_s(4),
      DOA(3) => H_thres_s(3),
      DOA(2) => H_thres_s(2),
      DOA(1) => H_thres_s(1),
      DOA(0) => H_thres_s(0),
      DOPA(1) => RAMB16_H_inst_DOPA1,
      DOPA(0) => RAMB16_H_inst_DOPA0,
      DOB(15) => RAMB16_H_inst_DOB15,
      DOB(14) => RAMB16_H_inst_DOB14,
      DOB(13) => RAMB16_H_inst_DOB13,
      DOB(12) => RAMB16_H_inst_DOB12,
      DOB(11) => RAMB16_H_inst_DOB11,
      DOB(10) => RAMB16_H_inst_DOB10,
      DOB(9) => RAMB16_H_inst_DOB9,
      DOB(8) => RAMB16_H_inst_DOB8,
      DOB(7) => RAMB16_H_inst_DOB7,
      DOB(6) => RAMB16_H_inst_DOB6,
      DOB(5) => RAMB16_H_inst_DOB5,
      DOB(4) => RAMB16_H_inst_DOB4,
      DOB(3) => RAMB16_H_inst_DOB3,
      DOB(2) => RAMB16_H_inst_DOB2,
      DOB(1) => RAMB16_H_inst_DOB1,
      DOB(0) => RAMB16_H_inst_DOB0,
      DOPB(1) => RAMB16_H_inst_DOPB1,
      DOPB(0) => RAMB16_H_inst_DOPB0
    );
  RAMB16_Y_inst : X_RAMB16_S18_S18
    generic map(
      INIT_A => X"00000",
      INIT_B => X"00000",
      SRVAL_A => X"00000",
      SRVAL_B => X"00000",
      SIM_COLLISION_CHECK => "ALL",
      WRITE_MODE_A => "WRITE_FIRST",
      WRITE_MODE_B => "WRITE_FIRST",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      LOC => "RAMB16_X1Y3",
      SETUP_ALL => 484 ps,
      SETUP_READ_FIRST => 484 ps
    )
    port map (
      CLKA => clk_i_BUFGP,
      CLKB => clk_i_BUFGP,
      ENA => GLOBAL_LOGIC1,
      ENB => Y_enable_B_s_0,
      SSRA => GLOBAL_LOGIC0,
      SSRB => GLOBAL_LOGIC0,
      WEA => GLOBAL_LOGIC0,
      WEB => GLOBAL_LOGIC1,
      ADDRA(9) => GLOBAL_LOGIC0,
      ADDRA(8) => Y_i_8_IBUF_458,
      ADDRA(7) => Y_i_7_IBUF_456,
      ADDRA(6) => Y_i_6_IBUF_454,
      ADDRA(5) => Y_i_5_IBUF_452,
      ADDRA(4) => Y_i_4_IBUF_450,
      ADDRA(3) => Y_i_3_IBUF_448,
      ADDRA(2) => Y_i_2_IBUF_446,
      ADDRA(1) => Y_i_1_IBUF_442,
      ADDRA(0) => Y_i_0_IBUF_439,
      ADDRB(9) => GLOBAL_LOGIC0,
      ADDRB(8) => adress_i_8_IBUF_410,
      ADDRB(7) => adress_i_7_IBUF_408,
      ADDRB(6) => adress_i_6_IBUF_407,
      ADDRB(5) => adress_i_5_IBUF_406,
      ADDRB(4) => adress_i_4_IBUF_405,
      ADDRB(3) => adress_i_3_IBUF_404,
      ADDRB(2) => adress_i_2_IBUF_465,
      ADDRB(1) => adress_i_1_IBUF_464,
      ADDRB(0) => adress_i_0_IBUF_463,
      DIA(15) => RAMB16_Y_inst_DIA15,
      DIA(14) => RAMB16_Y_inst_DIA14,
      DIA(13) => RAMB16_Y_inst_DIA13,
      DIA(12) => RAMB16_Y_inst_DIA12,
      DIA(11) => RAMB16_Y_inst_DIA11,
      DIA(10) => RAMB16_Y_inst_DIA10,
      DIA(9) => RAMB16_Y_inst_DIA9,
      DIA(8) => RAMB16_Y_inst_DIA8,
      DIA(7) => RAMB16_Y_inst_DIA7,
      DIA(6) => RAMB16_Y_inst_DIA6,
      DIA(5) => RAMB16_Y_inst_DIA5,
      DIA(4) => RAMB16_Y_inst_DIA4,
      DIA(3) => RAMB16_Y_inst_DIA3,
      DIA(2) => RAMB16_Y_inst_DIA2,
      DIA(1) => RAMB16_Y_inst_DIA1,
      DIA(0) => RAMB16_Y_inst_DIA0,
      DIPA(1) => RAMB16_Y_inst_DIPA1,
      DIPA(0) => RAMB16_Y_inst_DIPA0,
      DIB(15) => value_i_15_IBUF_420,
      DIB(14) => value_i_14_IBUF_418,
      DIB(13) => value_i_13_IBUF_416,
      DIB(12) => value_i_12_IBUF_414,
      DIB(11) => value_i_11_IBUF_411,
      DIB(10) => value_i_10_IBUF_409,
      DIB(9) => value_i_9_IBUF_443,
      DIB(8) => value_i_8_IBUF_440,
      DIB(7) => value_i_7_IBUF_437,
      DIB(6) => value_i_6_IBUF_435,
      DIB(5) => value_i_5_IBUF_433,
      DIB(4) => value_i_4_IBUF_431,
      DIB(3) => value_i_3_IBUF_430,
      DIB(2) => value_i_2_IBUF_428,
      DIB(1) => value_i_1_IBUF_427,
      DIB(0) => value_i_0_IBUF_426,
      DIPB(1) => GLOBAL_LOGIC0,
      DIPB(0) => GLOBAL_LOGIC0,
      DOA(15) => Y_thres_s(15),
      DOA(14) => Y_thres_s(14),
      DOA(13) => Y_thres_s(13),
      DOA(12) => Y_thres_s(12),
      DOA(11) => Y_thres_s(11),
      DOA(10) => Y_thres_s(10),
      DOA(9) => Y_thres_s(9),
      DOA(8) => Y_thres_s(8),
      DOA(7) => Y_thres_s(7),
      DOA(6) => Y_thres_s(6),
      DOA(5) => Y_thres_s(5),
      DOA(4) => Y_thres_s(4),
      DOA(3) => Y_thres_s(3),
      DOA(2) => Y_thres_s(2),
      DOA(1) => Y_thres_s(1),
      DOA(0) => Y_thres_s(0),
      DOPA(1) => RAMB16_Y_inst_DOPA1,
      DOPA(0) => RAMB16_Y_inst_DOPA0,
      DOB(15) => RAMB16_Y_inst_DOB15,
      DOB(14) => RAMB16_Y_inst_DOB14,
      DOB(13) => RAMB16_Y_inst_DOB13,
      DOB(12) => RAMB16_Y_inst_DOB12,
      DOB(11) => RAMB16_Y_inst_DOB11,
      DOB(10) => RAMB16_Y_inst_DOB10,
      DOB(9) => RAMB16_Y_inst_DOB9,
      DOB(8) => RAMB16_Y_inst_DOB8,
      DOB(7) => RAMB16_Y_inst_DOB7,
      DOB(6) => RAMB16_Y_inst_DOB6,
      DOB(5) => RAMB16_Y_inst_DOB5,
      DOB(4) => RAMB16_Y_inst_DOB4,
      DOB(3) => RAMB16_Y_inst_DOB3,
      DOB(2) => RAMB16_Y_inst_DOB2,
      DOB(1) => RAMB16_Y_inst_DOB1,
      DOB(0) => RAMB16_Y_inst_DOB0,
      DOPB(1) => RAMB16_Y_inst_DOPB1,
      DOPB(0) => RAMB16_Y_inst_DOPB0
    );
  result_o_1_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(1),
      O => result_o_1_DXMUX_1142
    );
  result_o_1_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(0),
      O => result_o_1_DYMUX_1129
    );
  result_o_1_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y24",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_1_CLKINV_1119
    );
  result_o_and0000_0_1 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X34Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_thres_s(0),
      ADR2 => H_thres_s(0),
      ADR3 => VCC,
      O => result_o_and0000(0)
    );
  result_o_3_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X35Y30",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(3),
      O => result_o_3_DXMUX_1176
    );
  result_o_3_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X35Y30",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(2),
      O => result_o_3_DYMUX_1163
    );
  result_o_3_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X35Y30",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_3_CLKINV_1153
    );
  result_o_and0000_2_1 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X35Y30"
    )
    port map (
      ADR0 => Y_thres_s(2),
      ADR1 => H_thres_s(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => result_o_and0000(2)
    );
  result_o_5_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X35Y32",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(5),
      O => result_o_5_DXMUX_1210
    );
  result_o_5_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X35Y32",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(4),
      O => result_o_5_DYMUX_1197
    );
  result_o_5_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X35Y32",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_5_CLKINV_1187
    );
  result_o_and0000_4_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X35Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(4),
      ADR2 => VCC,
      ADR3 => Y_thres_s(4),
      O => result_o_and0000(4)
    );
  result_o_7_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y34",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(7),
      O => result_o_7_DXMUX_1244
    );
  result_o_7_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y34",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(6),
      O => result_o_7_DYMUX_1231
    );
  result_o_7_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y34",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_7_CLKINV_1221
    );
  result_o_and0000_6_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X34Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(6),
      ADR2 => VCC,
      ADR3 => Y_thres_s(6),
      O => result_o_and0000(6)
    );
  result_o_9_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y36",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(9),
      O => result_o_9_DXMUX_1278
    );
  result_o_9_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y36",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(8),
      O => result_o_9_DYMUX_1265
    );
  result_o_9_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y36",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_9_CLKINV_1255
    );
  result_o_and0000_8_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X34Y36"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(8),
      ADR2 => VCC,
      ADR3 => Y_thres_s(8),
      O => result_o_and0000(8)
    );
  result_o_11_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y37",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(11),
      O => result_o_11_DXMUX_1312
    );
  result_o_11_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y37",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(10),
      O => result_o_11_DYMUX_1299
    );
  result_o_11_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y37",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_11_CLKINV_1289
    );
  result_o_and0000_10_1 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X34Y37"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(10),
      ADR2 => Y_thres_s(10),
      ADR3 => VCC,
      O => result_o_and0000(10)
    );
  result_o_13_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y38",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(13),
      O => result_o_13_DXMUX_1346
    );
  result_o_13_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y38",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(12),
      O => result_o_13_DYMUX_1333
    );
  result_o_13_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y38",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_13_CLKINV_1323
    );
  result_o_and0000_12_1 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X34Y38"
    )
    port map (
      ADR0 => H_thres_s(12),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => Y_thres_s(12),
      O => result_o_and0000(12)
    );
  result_o_15_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y39",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(15),
      O => result_o_15_DXMUX_1380
    );
  result_o_15_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X34Y39",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_and0000(14),
      O => result_o_15_DYMUX_1367
    );
  result_o_15_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X34Y39",
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_i_BUFGP,
      O => result_o_15_CLKINV_1357
    );
  result_o_and0000_14_1 : X_LUT4
    generic map(
      INIT => X"C0C0",
      LOC => "SLICE_X34Y39"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(14),
      ADR2 => Y_thres_s(14),
      ADR3 => VCC,
      O => result_o_and0000(14)
    );
  Y_enable_B_s_XUSED : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_enable_B_s,
      O => Y_enable_B_s_0
    );
  Y_enable_B_s_YUSED : X_BUF
    generic map(
      LOC => "SLICE_X38Y27",
      PATHPULSE => 757 ps
    )
    port map (
      I => H_enable_B_s,
      O => H_enable_B_s_0
    );
  H_enable_B_s1 : X_LUT4
    generic map(
      INIT => X"00CC",
      LOC => "SLICE_X38Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => valid_i_IBUF_462,
      ADR2 => VCC,
      ADR3 => adress_i_9_IBUF_412,
      O => H_enable_B_s
    );
  result_o_0 : X_FF
    generic map(
      LOC => "SLICE_X34Y24",
      INIT => '0'
    )
    port map (
      I => result_o_1_DYMUX_1129,
      CE => VCC,
      CLK => result_o_1_CLKINV_1119,
      SET => GND,
      RST => GND,
      O => result_o_0_444
    );
  result_o_and0000_1_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X34Y24"
    )
    port map (
      ADR0 => VCC,
      ADR1 => H_thres_s(1),
      ADR2 => VCC,
      ADR3 => Y_thres_s(1),
      O => result_o_and0000(1)
    );
  result_o_1 : X_FF
    generic map(
      LOC => "SLICE_X34Y24",
      INIT => '0'
    )
    port map (
      I => result_o_1_DXMUX_1142,
      CE => VCC,
      CLK => result_o_1_CLKINV_1119,
      SET => GND,
      RST => GND,
      O => result_o_1_447
    );
  result_o_2 : X_FF
    generic map(
      LOC => "SLICE_X35Y30",
      INIT => '0'
    )
    port map (
      I => result_o_3_DYMUX_1163,
      CE => VCC,
      CLK => result_o_3_CLKINV_1153,
      SET => GND,
      RST => GND,
      O => result_o_2_449
    );
  result_o_and0000_3_1 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X35Y30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Y_thres_s(3),
      ADR3 => H_thres_s(3),
      O => result_o_and0000(3)
    );
  result_o_3 : X_FF
    generic map(
      LOC => "SLICE_X35Y30",
      INIT => '0'
    )
    port map (
      I => result_o_3_DXMUX_1176,
      CE => VCC,
      CLK => result_o_3_CLKINV_1153,
      SET => GND,
      RST => GND,
      O => result_o_3_451
    );
  result_o_4 : X_FF
    generic map(
      LOC => "SLICE_X35Y32",
      INIT => '0'
    )
    port map (
      I => result_o_5_DYMUX_1197,
      CE => VCC,
      CLK => result_o_5_CLKINV_1187,
      SET => GND,
      RST => GND,
      O => result_o_4_453
    );
  result_o_and0000_5_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X35Y32"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_thres_s(5),
      ADR2 => VCC,
      ADR3 => H_thres_s(5),
      O => result_o_and0000(5)
    );
  result_o_5 : X_FF
    generic map(
      LOC => "SLICE_X35Y32",
      INIT => '0'
    )
    port map (
      I => result_o_5_DXMUX_1210,
      CE => VCC,
      CLK => result_o_5_CLKINV_1187,
      SET => GND,
      RST => GND,
      O => result_o_5_455
    );
  result_o_6 : X_FF
    generic map(
      LOC => "SLICE_X34Y34",
      INIT => '0'
    )
    port map (
      I => result_o_7_DYMUX_1231,
      CE => VCC,
      CLK => result_o_7_CLKINV_1221,
      SET => GND,
      RST => GND,
      O => result_o_6_457
    );
  Y_enable_B_s1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X38Y27"
    )
    port map (
      ADR0 => VCC,
      ADR1 => valid_i_IBUF_462,
      ADR2 => VCC,
      ADR3 => adress_i_9_IBUF_412,
      O => Y_enable_B_s
    );
  result_o_and0000_7_1 : X_LUT4
    generic map(
      INIT => X"CC00",
      LOC => "SLICE_X34Y34"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Y_thres_s(7),
      ADR2 => VCC,
      ADR3 => H_thres_s(7),
      O => result_o_and0000(7)
    );
  result_o_7 : X_FF
    generic map(
      LOC => "SLICE_X34Y34",
      INIT => '0'
    )
    port map (
      I => result_o_7_DXMUX_1244,
      CE => VCC,
      CLK => result_o_7_CLKINV_1221,
      SET => GND,
      RST => GND,
      O => result_o_7_459
    );
  result_o_8 : X_FF
    generic map(
      LOC => "SLICE_X34Y36",
      INIT => '0'
    )
    port map (
      I => result_o_9_DYMUX_1265,
      CE => VCC,
      CLK => result_o_9_CLKINV_1255,
      SET => GND,
      RST => GND,
      O => result_o_8_460
    );
  result_o_and0000_9_1 : X_LUT4
    generic map(
      INIT => X"AA00",
      LOC => "SLICE_X34Y36"
    )
    port map (
      ADR0 => Y_thres_s(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => H_thres_s(9),
      O => result_o_and0000(9)
    );
  result_o_9 : X_FF
    generic map(
      LOC => "SLICE_X34Y36",
      INIT => '0'
    )
    port map (
      I => result_o_9_DXMUX_1278,
      CE => VCC,
      CLK => result_o_9_CLKINV_1255,
      SET => GND,
      RST => GND,
      O => result_o_9_461
    );
  result_o_10 : X_FF
    generic map(
      LOC => "SLICE_X34Y37",
      INIT => '0'
    )
    port map (
      I => result_o_11_DYMUX_1299,
      CE => VCC,
      CLK => result_o_11_CLKINV_1289,
      SET => GND,
      RST => GND,
      O => result_o_10_432
    );
  result_o_and0000_11_1 : X_LUT4
    generic map(
      INIT => X"A0A0",
      LOC => "SLICE_X34Y37"
    )
    port map (
      ADR0 => H_thres_s(11),
      ADR1 => VCC,
      ADR2 => Y_thres_s(11),
      ADR3 => VCC,
      O => result_o_and0000(11)
    );
  result_o_11 : X_FF
    generic map(
      LOC => "SLICE_X34Y37",
      INIT => '0'
    )
    port map (
      I => result_o_11_DXMUX_1312,
      CE => VCC,
      CLK => result_o_11_CLKINV_1289,
      SET => GND,
      RST => GND,
      O => result_o_11_434
    );
  result_o_12 : X_FF
    generic map(
      LOC => "SLICE_X34Y38",
      INIT => '0'
    )
    port map (
      I => result_o_13_DYMUX_1333,
      CE => VCC,
      CLK => result_o_13_CLKINV_1323,
      SET => GND,
      RST => GND,
      O => result_o_12_436
    );
  result_o_and0000_13_1 : X_LUT4
    generic map(
      INIT => X"8888",
      LOC => "SLICE_X34Y38"
    )
    port map (
      ADR0 => Y_thres_s(13),
      ADR1 => H_thres_s(13),
      ADR2 => VCC,
      ADR3 => VCC,
      O => result_o_and0000(13)
    );
  result_o_13 : X_FF
    generic map(
      LOC => "SLICE_X34Y38",
      INIT => '0'
    )
    port map (
      I => result_o_13_DXMUX_1346,
      CE => VCC,
      CLK => result_o_13_CLKINV_1323,
      SET => GND,
      RST => GND,
      O => result_o_13_438
    );
  result_o_14 : X_FF
    generic map(
      LOC => "SLICE_X34Y39",
      INIT => '0'
    )
    port map (
      I => result_o_15_DYMUX_1367,
      CE => VCC,
      CLK => result_o_15_CLKINV_1357,
      SET => GND,
      RST => GND,
      O => result_o_14_441
    );
  result_o_and0000_15_1 : X_LUT4
    generic map(
      INIT => X"F000",
      LOC => "SLICE_X34Y39"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => Y_thres_s(15),
      ADR3 => H_thres_s(15),
      O => result_o_and0000(15)
    );
  result_o_15 : X_FF
    generic map(
      LOC => "SLICE_X34Y39",
      INIT => '0'
    )
    port map (
      I => result_o_15_DXMUX_1380,
      CE => VCC,
      CLK => result_o_15_CLKINV_1357,
      SET => GND,
      RST => GND,
      O => result_o_15_445
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  GLOBAL_LOGIC0_GND : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  result_o_10_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD50",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_10_432,
      O => result_o_10_O
    );
  result_o_11_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD49",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_11_434,
      O => result_o_11_O
    );
  result_o_12_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD39",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_12_436,
      O => result_o_12_O
    );
  result_o_13_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD38",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_13_438,
      O => result_o_13_O
    );
  result_o_14_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD37",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_14_441,
      O => result_o_14_O
    );
  result_o_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD75",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_0_444,
      O => result_o_0_O
    );
  result_o_15_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD52",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_15_445,
      O => result_o_15_O
    );
  result_o_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD74",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_1_447,
      O => result_o_1_O
    );
  result_o_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD180",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_2_449,
      O => result_o_2_O
    );
  result_o_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD179",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_3_451,
      O => result_o_3_O
    );
  result_o_4_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD20",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_4_453,
      O => result_o_4_O
    );
  result_o_5_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD181",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_5_455,
      O => result_o_5_O
    );
  result_o_6_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD13",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_6_457,
      O => result_o_6_O
    );
  result_o_7_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD30",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_7_459,
      O => result_o_7_O
    );
  result_o_8_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD3",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_8_460,
      O => result_o_8_O
    );
  result_o_9_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD2",
      PATHPULSE => 757 ps
    )
    port map (
      I => result_o_9_461,
      O => result_o_9_O
    );
  NlwBlock_threshold_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_threshold_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

